June 11, 2018 -- MIPS, provider of the widely used MIPS processor architecture and IP cores for licensing, today announced that its I6500-F CPU IP core, designed as a Safety Element out of Context ...
Within our advanced EyeQ®5 SoC, MIPS I6500 cores are coherently coupled with Mobileye’s Vision Processors supported by NetSpeed’s Gemini cache coherent interconnect IP. The resulting solution will ...
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